1. Field of the Invention
The present invention relates to semiconductor structures and, more particular to gate overvoltage control networks that can be used in semiconductor structures to protect the various gated devices present therein from exhibiting overvoltage conditions which may lead to early electrostatic discharge (ESD) failures. In some cases, the gate overvoltage control network of the present invention may be used to protect gated devices from undergoing charged device model (CDM) ESD failures.
2. Background of the Invention
In semiconductor processing, SOI (silicon-on-insulator) technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, e.g., Si, overlays a layer of insulating material (buried oxide region). This relatively thin layer of semiconducting material is generally the area wherein active devices are formed in SOI devices. Devices formed on SOI offer many advantages over their bulk Si counterparts, including higher performance, absence of latch-up, higher packing density and low voltage applications.
Despite the advantages obtained using SOI technology, SOI circuits, like other electronic devices, are susceptible to electrostatic discharge (ESD), i.e., a surge in voltage (negative or positive) that occurs when large amount of current is applied in the circuit. Moreover, the handling of SOI devices themselves may lead to charging of the substrate.
To discharge electrostatic impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diodes, do not work well on SOI because of the presence of the relatively thin SOI buried oxide layer. That is, conventional diodes on SOI devices have small current drivability because the current is carried laterally (limited by the thickness of the semiconductor material).
One approach for protecting SOI circuitry from ESD is found in U.S. Pat. No. 4,989,057 to Lu. Lu discloses a gated diode, which could be used for ESD design. The gated diode disclosed in Lu consists of a floating-body SOI transistor, with the gate connected to a signal pad. Although the diode disclosed in Lu can provide some ESD protection, the disclosed diode does not allow for obtaining ideal diode characteristics. Some reasons preventing ideal diode characteristics with the diodes disclosed in Lu include: (1) alignment tolerance of the substrate causes large process-induced variations; and (2) the conventional diode structure may be a polysilicon diode, which receives extensions and halo implants (implants normally utilized in deep sub-micron MOSFETs) that degrade the ideal characteristics on SOI. Other ESD protection schemes for the front side of the SOI wafer are also known. Common to each is that the energy developed across prior art ESD protection schemes can be substantial. Thus, the heat generated by such ESD protection schemes must be dissipated by the relatively thin semiconducting layer. In cases wherein the heat becomes too excessive, destruction of the SOI circuit may occur.
Another problem with prior art ESD networks is that under some operating conditions the various gated devices in which the ESD networks are suppose to protect undergo overvoltage conditions which may lead to early ESD failures. This problem is not limited to SOI devices. Instead, it exists in bulk Si devices as well.
Another problem with prior art ESD protection schemes is that they do not adequately eliminate charged device model (CDM) failure mechanism. In receiver circuits in SOI technology, experimental work has shown that N-channel metal oxide semiconductor field effect transistors (MOSFETs) fail due to current flowing in from the Vdd power supply through the gate of the MOSFET causing MOSFET failure.
To date, no adequate control network has been developed that can be used in semiconductor structures to prevent the various gated devices present therein from exhibiting the above mentioned problems. There is thus a great need for developing a control network that can substantially eliminate overvoltage and/or avoid CDM ESD failures in the various gated devices present in semiconductor structures.
In one aspect, the present invention provides an overvoltage control network that can be implemented in various semiconductor structures, including SOI devices and bulk Si devices, that contain at least one gated device therein.
In yet another aspect, the present invention provides an overvoltage control network that is capable of reducing overvoltage, electrical stress, tunneling current, ESD, and CDM failure mechanism in various semiconductor structures which include at least one gated device region therein.
In another aspect, the present invention provides an overvoltage control network that can be used with diodes such as polysilicon diodes; buried resistors; resistors; transistors such as MOSFET, PFETs and NFETs; or other gated devices in which an overvoltage condition may cause device failure.
These and other advantages are achieved in the present invention by providing an overvoltage control network that is coupled to the gate of a gated device region that is present in a semiconductor structure.
Specifically, the present invention provides a semiconductor structure which comprises: an anode of a first conductivity type; a cathode of a second conductivity type; a device region separating said anode and said cathode, said device region including at least a dielectric gate; and an overvoltage control network coupled to the dielectric gate of said device region, wherein said overvoltage control network substantially reduces electrical overstress of said dielectric gate in said device region.
The term xe2x80x9cdevice regionxe2x80x9d is used herein to denote a gated device region in which a dielectric layer separates a gate conductor from active areas that are present in a semiconductor substrate (bulk Si, Ge, III/V semiconductor compounds such as InAs, SiGe, GaAs and SiGe, silicon-on-insulators (SOIs), layered semiconductors such as Si/SiGe). Examples of suitable gated devices that can be employed in the present invention include, but are not limited to: diodes, resistors, buried resistors, MOSFETs, NFETs, PFETs and other like gated devices.
The term xe2x80x9canodexe2x80x9d is used herein to denote an electron-collecting region, i.e., electron deficient region, of a semiconductor structure. Examples of anode regions include, but are not limited to: drain regions, positive terminals of a power supply and output terminals of an integrated circuit.
The term xe2x80x9ccathodexe2x80x9d is used herein to denote an electron-donating region, i.e., electron rich region, of a semiconductor structure. Examples of cathode regions include, but are not limited to: source regions, negative terminals of a power supply, pad regions and input terminals of an integrated circuits.
The term xe2x80x9covervoltage control networkxe2x80x9d is used herein to denote any network that is capable of reducing electrical overstress that may exist in a gated device region of a semiconductor structure. The overvoltage control network used in the present invention must be capable of being directly coupled to a gate dielectric layer present in the gated device region. Examples of suitable overvoltage control networks that can be employed in the present invention include, but are not limited to: diodes, resistors, buried resistors, dividers, on-MOSFETs, MOSFET voltage dividers, dummy inverters, lubistors, and other like control networks that can reduce electrical overstress of said gated device region. Combinations of one or more of these overvoltage control networks are also contemplated in the present invention.
The overvoltage control network may be connected to various external power supplies as well as the anode and cathode mentioned above. The overvoltage control network can also be used in conjunction with other ESD protection networks that are well known to those skilled in the art.
In one highly preferred embodiment of the present invention, the structure comprises a buried resistor that is formed in a bulk semiconducting substrate or a SOI substrate, said buried resistor having a dielectric gate and being located between an anode and a cathode, and an overvoltage control network coupled to the dielectric gate of said buried resistor, said overvoltage control network being coupled to two different power supplies.
In this embodiment of the present invention, the overvoltage control network may comprise a MOSFET voltage divider wherein the MOSFETs are in an xe2x80x9conxe2x80x9d state. In a bulk implementation, using PFETs, the wells of the network are either floating well elements to avoid clamping to the ground or Vdd power supplies. Alternatively, the network can comprise well-bias control elements to avoid clamping of the buried resistors. The overvoltage control networks are established to avoid d.c. current paths between Vdd and Vss power supplies.
The buried resistor structure may also use a non-voltage divider network as the overvoltage control network. When a non-voltage network is used, it typically consists of a network that sets the potential for standard functional states and lets the network float in unpowered states. For example, an NFET can be used below a voltage divider network whose gate is connected to Vdd. When the chip is pulsed negatively, the Vdd is unpowered and the NFET is off. This allows the overvoltage control network to float and avoid overvoltage.
Another means of setting the gate potential of the buried resistor is to connect the buried resistor gate through a resistor prior to the power supply voltage. This would permit the gate to couple to the input pad for positive or negative voltages. If the resistor element is of the order of 1 kOhm, then the pad voltage will allow the gate of the resistor to follow the pad potential and decouple from the Vdd power supply. Another means of power supply decoupling in the buried resistor embodiment of the present invention is to use a dummy inverter as the overvoltage control network to set the potential of the gate of the buried resistor. The inverter can also be followed by a resistor so that there is no current path back to a power supply at fast time scales. For example, the input of the inverter can be connected to ground via a resistor providing a xe2x80x9clowxe2x80x9d. This is then inverted to a xe2x80x9chighxe2x80x9d to the gate of the buried resistor. A resistor can exist between the buried resistor gate and the inverter. For ESD pulses, the gate will float with positive and negative pulses and will not be connected directly to a pad node.
In another highly preferred embodiment of the present invention, the gated device is a polysilicon gated diode that is formed on a bulk semiconductor substrate or on an SOI substrate. In such a gated device, the gated diode is typically connected between the pad and the Vcc power supply. A first network to solve overstress in such a gated device includes a first and second NFET in series, wherein the first NFET is connected between the Vcc and the second NFET. The gate of the first NFET is such that the first NFET is xe2x80x9conxe2x80x9d, i.e., gate tied to Vcc. The second NFET has its gate connected to pad, the source and body connected together which in turn is connected to the polysilicon gate of the gated diode device.
When the pad is low, the second NFET is xe2x80x9coffxe2x80x9d, allowing the gate of the polysilicon diode device to float. This prevents the electrical overstress from occurring between the pad and the gate of the polysilicon diode. When the gate is xe2x80x9chighxe2x80x9d, the NFET is xe2x80x9conxe2x80x9d, and the gate follows the power supply voltage to Vcc.
For a gated diode connected between the pad and the ground connection, a similar control network can be used. In this case, a first and second PFET are employed. The first PFET acts to reduce the voltage stress across the second PFET in series. The first PFET is connected between the second PFET and the ground. The gate of the first PFET is xe2x80x9conxe2x80x9d acting as a pass transistor voltage reducing element. The second PFET is connected with the gate connected to the pad node; the well and source are connected together and then these nodes are also connected to the polysilicon gate of the diode element. When the pad is xe2x80x9chighxe2x80x9d, the second PFET is xe2x80x9coffxe2x80x9d allowing the gate node of the polysilicon diode to float with the input node. When the pad is xe2x80x9clowxe2x80x9d, the PFET is xe2x80x9conxe2x80x9d, and the anode, cathode and the gate of the polysilicon diode have no voltage stress.
In the above embodiment concerning a polysilicon gated diode, the first transistor element (NFET or PFET) can be replaced with a buried resistor, a resistor or a plurality of other elements that act as a voltage reduction means as well as serving the role as sourcing the current to the polysilicon gated diode controller elements.
In another highly preferred embodiment of the present invention, the gated device is a N-channel MOSFET pass transistor. In such systems, CDM events cause ESD failures due to current flowing in from the Vdd power supply through the gate causing MOSFET failure. In one embodiment, the overvoltage control network is a resistor which prevents current flowing from the Vdd due to a CDM event. The presence of the resistor in such a structure also prevents tunneling gate current from charging the body of the pass transistor for thin and ultra-thin dielectrics.
In the N-channel MOSFET pass device, the overvoltage control network may also be a buried resistor, with the gate thereof connected to Vdd to prevent electrical overstress. Other possible overvoltage control networks that can be used in this embodiment of the present invention include: dummy inverters and dummy inverters and a SOI MOSFET connected in a resistor configuration.
The foregoing and other advantages and features of the present invention will be apparent from the following more particularly preferred embodiments of the present invention, as illustrated in the drawings and described hereinbelow.